LLM Hardware Generator

LLM-based Hardware Verification

An automated pipeline for generating hardware designs and verification tests using Large Language Models. Transform natural language specifications into Verilog code and BDD test scenarios.

🤖

Multi-LLM Support

GPT, Claude, Gemini, Groq, DeepSeek

⚡

Automated Pipeline

DUT → BDD → Testbench

📊

Quality Analysis

Coverage & comparison reports

1 Hardware

→

2 BDD Tests

→

3 Testbench

→

4 Simulation

Hardware → Tests: Write hardware first, then generate tests to verify it Current

🔧 Hardware Design (DUV)

Generate with LLM or upload existing Verilog file

Pending

▼

⚡ Configuration

Module Type

Bitwidth

Registers

Pipeline

LLM Provider

Model

or use natural language

Natural Language Input

Examples:

16-bit ALU 32-bit Counter 32x32 RegFile RISC-V CPU

⚡ Stream output

Generating...

✅

Generating...

Ready to generate

LLM

Verilog Code Preview

🔬

Yosys Synthesis Analysis

▼

Running Yosys synthesis...

📁

Drag & drop your Verilog file here

or click to browse

📄 .v, .sv files

📏 Max 1MB

🔒 Secure upload

📄

alu_16bit.v

2.3 KB • Uploaded successfully

Module Name alu_16bit

Detected Type ALU High

Bitwidth 16-bit

Pipeline Stages 5-stage

Registers 32 registers

Inputs clk, rst_n, A, B, opcode

Outputs result, zero, overflow

🔧 Adjust Detection (Optional)

Module Type

Bitwidth Override

Pipeline Override

Registers Override

🔬

Yosys Synthesis Analysis

▼

Running Yosys synthesis...

🧪 BDD Specification Scenarios

Generate with LLM or upload existing .feature file

Pending

▼

📋

Current DUT

- • - • -

LLM

⚠️

No Hardware Generated

Complete Step 1 first to generate or upload hardware.

⚡ Configuration

LLM Provider

Requirements (auto-filled based on DUT)

Examples:

Basic test Boundary Reset

⚡ Stream output

Generating...

✅

Generating...

Ready to generate

LLM

BDD Feature Preview

📄

Drag & drop your BDD feature file here

or click to browse

📄 .feature files

📏 Max 1MB

🔒 Secure upload

📄

test.feature

2.3 KB • Uploaded successfully

Feature Name -

Scenarios 0

📋 File Preview

⚙️ Verilog Testbench

Generate from BDD or upload existing testbench

Pending

▼

📄

Source BDD

- • -

⚠️

No BDD File Generated

Complete Step 2 first to generate BDD test scenarios.

⚡ Configuration

Generation Mode

DUT Module Name

Bitwidth

Registers

Pipeline

✅

Generating...

Ready to generate

Quality Score - -

Test Cases -

Operations Covered -

Corner Cases -

Testbench Preview

✅

Batch Generation Complete

BATCH

Total Testbenches -

LLM Providers -

Results by LLM

📄

Drag & drop your Verilog testbench file here

or click to browse

📄 .v, .sv files

📏 Max 1MB

🔒 Secure upload

📄

testbench.v

4.5 KB • Uploaded successfully

Module Name -

Test Count (estimated) 0

📋 File Preview

🚀 Run Simulation

Execute testbench and view results

Pending

▼

🔧

Simulation Tools

Checking...

...

⚠️

No Testbench Available

Complete Step 3 first to generate a testbench.

⚡ Configuration

Simulation Mode

Testbench -

DUT -

✅

Simulation Complete

SIM

Total Tests -

Passed -

Failed -

Pass Rate - -

Compile Time -

Simulation Time -

📋 Simulation Log

💡 How to view waveform:
1. Download the .vcd file above
2. Open with GTKWave (free tool)
3. Or run:

gtkwave
                    filename.vcd

✅

Batch Simulation Complete

BATCH

Total Simulations -

Successful -

Overall Pass Rate -

Results by LLM

🔒 Privacy Policy (Datenschutzerklärung)

General Information

This website is a non-commercial academic research project operated by the University of Bremen, Group of Computer Architecture (AGRA).

Access Data and Server Logs

When accessing this website, the hosting provider may automatically process technical information such as IP address, browser type, operating system, date and time of access, and referrer URL. This data is processed solely for the purpose of ensuring system security, stability, and error analysis.

Legal Basis

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External Links (GitHub and arXiv)

This website contains links to external services, including GitHub and arXiv. When clicking on these links, you leave this website. The respective privacy policies of GitHub and arXiv apply. No personal data is transmitted to these platforms by this website itself unless you actively follow the provided links.

Data Retention

Personal data is stored only for as long as necessary to fulfill the purposes described above and in accordance with applicable legal obligations.

Rights of Data Subjects

You have the right to request information about the personal data processed, as well as the right to rectification, erasure, restriction of processing, data portability, and to object to processing, in accordance with Articles 15–21 GDPR.

Contact for Data Protection

For any questions regarding data protection, please contact:
📧 treebush302@gmail.com

LLM-based Hardware Verification

🤖 LLM Hardware Verification

Generating...

Yosys Synthesis Analysis

alu_16bit.v

Yosys Synthesis Analysis

Current DUT

No Hardware Generated

Generating...

test.feature

Source BDD

No BDD File Generated

Generating...

Batch Generation Complete

testbench.v

Simulation Tools

No Testbench Available

Simulation Tools Not Available

Simulation Complete

Batch Simulation Complete

LLM-based Hardware Verification

🤖 LLM Hardware Verification

Generating...

Yosys Synthesis Analysis

alu_16bit.v

Yosys Synthesis Analysis

Current DUT

No Hardware Generated

Generating...

test.feature

Source BDD

No BDD File Generated

Generating...

Batch Generation Complete

testbench.v

Simulation Tools

No Testbench Available

Simulation Tools Not Available

Simulation Complete

Batch Simulation Complete

📊 Quality Comparison Report

📜 Imprint / Legal Notice

Institution

Contact

Responsible for Content (according to §55(2) RStV)

Research Disclaimer

Liability for Content

Liability for Links (GitHub / arXiv)

Copyright

🔒 Privacy Policy (Datenschutzerklärung)

General Information

Access Data and Server Logs

Legal Basis

External Links (GitHub and arXiv)

Data Retention

Rights of Data Subjects

Contact for Data Protection

🔐 Developer Access